Lithographic apparatuses can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”. Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit. Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask).
As noted, microlithography is a central step in the manufacturing of semiconductor integrated circuits, where patterns formed on semiconductor wafer substrates define the functional elements of semiconductor devices, such as microprocessors, memory chips etc. Similar lithographic techniques are also used in the formation of flat panel displays, micro-electro mechanical systems (MEMS) and other devices.
As semiconductor manufacturing processes continue to advance, the dimensions of circuit elements have continually been reduced while the amount of functional elements, such as transistors, per device has been steadily increasing over decades, following a trend commonly referred to as “Moore's law”. At the current state of technology, critical layers of leading-edge devices are manufactured using optical lithographic projection systems known as scanners that project a mask image onto a substrate using illumination from a deep-ultraviolet laser light source, creating individual circuit features having dimensions well below 100 nm, i.e. less than half the wavelength of the projection light. Even in the case of extreme ultraviolet (EUV) imaging with a wavelength of about 13.5 nm, an accurate model must capture the resist effects.
This process, in which features with dimensions smaller than the classical resolution limit of an optical projection system are printed, is commonly known as low-k1 lithography, according to the resolution formula CD=k1×λ/NA, where λ is the wavelength of radiation employed, NA is the numerical aperture of the projection optics, CD is the “critical dimension”—generally the smallest feature size printed—and k1 is an empirical resolution factor. In general, the smaller k1, the more difficult it becomes to reproduce a pattern on the wafer that resembles the shape and dimensions planned by a circuit designer in order to achieve particular electrical functionality and performance. To overcome these difficulties, sophisticated fine-tuning steps are applied to the projection system as well as to the mask design. These include, for example, but not limited to, optimization of NA and optical coherence settings, customized illumination schemes, use of phase shifting masks, optical proximity correction in the mask layout, or other methods generally defined as “resolution enhancement techniques” (RET).
As one important example, optical proximity correction (OPC, sometimes also referred to as “optical and process correction”) addresses the fact that the final size and placement of a printed feature on the wafer will not simply be a function of the size and placement of the corresponding feature on the mask. It is noted that the terms “mask” and “reticle” are utilized interchangeably herein. For the small feature sizes and high feature densities present on typical circuit designs, the position of a particular edge of a given feature will be influenced to a certain extent by the presence or absence of other adjacent features. These proximity effects arise from minute amounts of light coupled from one feature to another. Similarly, proximity effects may arise from diffusion and other chemical effects during post-exposure bake (PEB), resist development, and etching that generally follow lithographic exposure.
In order to ensure that the features are generated on a semiconductor substrate in accordance with the requirements of the given target circuit design, proximity effects need to be predicted utilizing sophisticated numerical models, and corrections or pre-distortions need to be applied to the design of the mask before successful manufacturing of high-end devices becomes possible. In a typical high-end design almost every feature edge requires some modification in order to achieve printed patterns that come sufficiently close to the target design. These modifications may include shifting or biasing of edge positions or line widths as well as application of “sub-resolution assist” features that are not intended to print themselves, but will affect the properties of an associated primary feature.
The application of model-based OPC to a target design requires good process models and considerable computational resources, given the many millions of features typically present in a chip design. The OPC is essentially a very large optimization problem. In the general case, there is no closed-form solution to this problem, and OPC vendors use an approximate, iterative process that does not always resolve all possible weaknesses on a layout. Therefore, post-OPC designs, i.e. mask layouts after application of all pattern modifications by OPC and any other RET's, need to be verified by design inspection, i.e. intensive full-chip simulation using calibrated numerical process models, in order to minimize the possibility of design flaws being built into the manufacturing of a mask set. This is driven by the enormous cost of making high-end mask sets, which run in the multi-million dollar range, as well as by the impact on turn-around time by reworking or repairing actual masks once they have been manufactured.
OPC and other RET verification may be based on numerical modeling systems and methods, and commercial products are available based on the computational lithography (“CL”) techniques that are developed for generic or specific lithography machines.
OPC and other RET require robust models that describe the lithography process precisely. Calibration procedures for such lithography models are thus required that provide models being valid, robust and accurate across the process window. Currently, calibration is done using a certain number of 1-dimensional and/or 2-dimensional gauge patterns with wafer measurements. More specifically, those 1-dimensional gauge patterns include, but are not limited to, line-space patterns with varying pitch and CD, isolated lines, multiple lines, etc. and the 2-dimensional gauge patterns typically include line-ends, contacts, and randomly selected SRAM (Static Random Access Memory) patterns. Those skilled in the arts will understand that the present invention is generic enough to accommodate any type of pattern. These patterns are then imaged onto a wafer and resulting wafer CDs and/or contact energy are measured. The original gauge patterns and their wafer measurements are then used jointly to determine the model parameters which minimize the difference between model predictions and wafer measurements.
In current practice, the selection of gauge patterns is rather arbitrary. They may simply be chosen from experience or randomly chosen from the real circuit patterns. Such patterns are often insufficient for calibration or too computationally-intensive due to redundancy. In particular, for some parameters, all the patterns may be quite insensitive thus it may be difficult to determine the parameter values due to measurement inaccuracies. While on the other hand, many patterns may have very similar responses to parameter variations thus some of them are redundant and wafer measurements on these redundant patterns waste a lot of resources.
Meanwhile, CL models need to accurately predict the actual on-wafer pattern contours across a very large collection of possible geometric layout patterns. Therefore, both the proper choice of the model formulation to be employed and the accurate determination of values for all model parameters are very important.
Moreover, in the calibration of a CL model, wafer CD measurements for the selected test patterns are needed to optimize the model parameters. Collecting such metrology data is often time-consuming and expensive. In light of this effort, for the OPC application, these calibrations are typically done only once per technology node per target layer. For CL products in manufacturing, these calibrations need to be done for many scanners and on a somewhat regular basis. Therefore, model calibration procedures should address the issue of how to minimize the number of test structures that need to be measured without compromising the prediction accuracy of the resulting model.
Traditional approaches in model calibration aim primarily to provide a good description of the imaging behavior of those patterns that are known to be important to the physical circuit design community. Typically, this involves a substantial number of pattern types, each instantiated over an appropriate range of geometric variations. One of the most important examples is line CD versus pitch for the poly layer, for a number of frequently used transistor channel lengths (poly line CD) and from dense lines (minimum pitch) to isolated lines. However, in modern lithography, the optical range of influence (ambit) is much larger than the typical test structure and therefore it is no longer true that accurate modeling of a pre-selected number of relatively small test patterns guarantees accurate prediction of these patterns in their actual circuit environments. Most of the geometry-based approaches are somewhat heuristic in nature, and are often prone to one or both of the following drawbacks.
Firstly, the strong focus on predefined patterns means that there is no explicit consideration for proper coverage of model parameters and for guaranteeing that all the significant physical/chemical characteristics in a lithography process are suitably represented by these parameters. In the case of a model not based on first principle physics/chemistry, the predefined patterns similarly need to allow accurate calibration of the model's parameters. Due to a lack of discriminating patterns, patterns can be poorly determined or they can exhibit a high degree of degeneracy with other parameters. Either way, the methods routinely fail to properly describe the change in imaging behavior outside the conditions included in the model characterization.
Secondly, for some of the physical/chemical properties and associated model parameters that are captured by the calibration method, the approach is not economical and too many measurements provide essentially redundant information.
Thirdly, the current gauge selection methods are not easily generalizable. Every time a new gauge geometry is supplied, the user needs to establish new rules.
If a gauge selection is done using a purely non-geometry-based approach, then specific features of a given gauge are ignored.
Additionally, none of the traditional methods describe a comprehensive method to select the gauges once their characterization is done.
The increased use of computational lithography models outside their original conventional application in OPC implies that the model calibration procedures need to be adjusted also, such that the resulting models are at least: a) better in predicting imaging behavior for pattern types not included in the calibration test data, b) better in predicting imaging behavior for variations in the lithographic processing conditions (mask, scanner, resist, or etch related), and c) more frugal in terms of the amount of metrology needed. Accordingly, a need exists to address these and other shortfalls of the traditional methods.